A switched-mode power supply (SMPS) is typically chosen for an application when its weight, efficiency, size, or wide input range tolerance make it preferable to linear power supplies, and thus SMPSs are ubiquitous in consumer electronics, laboratory and medical equipment, scientific instruments, land, air (including the unmanned aerial vehicles (UAVs)), space, and naval vehicles, LED lighting, and central power distribution systems. Many of the SMPS markets are extremely high-volume (for example, tens of billions of units for portable low-power applications alone) and thus are very cost-sensitive, and the demands for both power efficiency requirements and cuts in the bill of materials (BOM) drive the use of the SMPSs and converters instead of linear power supplies.
An SMPS composed of ideal elements dissipates no power, and may also be substantially smaller and lighter than a respective linear supply. While having great advantages over linear regulators in efficiency, weight, size, and wide input range tolerance, switched-mode power supplies and converters, however, face a number of challenges that increase their complexity and cost, reduce reliability, complicate regulation, and limit their use in noise-sensitive applications.
An SMPS may be viewed as an electronic power supply (“converter”) that incorporates an active switch (“power switch”) that regulates either output voltage, or current, or power by switching storage elements, like inductors and capacitors, among different electrical configurations. The desired relation between the input (source) and the output of the supply may then be achieved by controlling the duration of the time intervals during which the switch is in its different positions.
In particular, a basic SMPS [4, 7, 10] may be viewed as an electronic power supply that incorporates a two-position power switch (e.g. a single pole double-throw switch (SPDT)) that alternates between positions 1 and 2 and regulates either output voltage or current by switching storage elements, like inductors and capacitors, between two different electrical configurations. The desired relation between the input (source) and the output of an SMPS may then be achieved by controlling the duration of the time intervals during which the switch is in position 1 or 2.
Let us denote the time instances at which the switch makes the transition from position 2 (“down”) to 1 (“up”) as “even” instances, and denote them as t2i, where i is an integer. Respectively, the time instances at which the switch makes the transition from position 1 (“up”) to 2 (“down”) would be “odd” instances, and may be denoted as t2i+1. Then the “up” (switch position 1) and “down” (switch position 2) time intervals may be expressed as Δt2i=t2i+1−t2i (“even”) and Δt2i+1=t2(i+1)−t2i+1 (“odd”), respectively. For convenience, we may denote an ith full switching interval Δt2i+Δt2i+1 as ΔTi, and may further define the respective “duty cycle” Di as
                              D          i                =                                            Δ              ⁢                                                          ⁢                              t                                  2                  ⁢                                                                          ⁢                  i                                                                                    Δ                ⁢                                                                  ⁢                                  t                                      2                    ⁢                                                                                  ⁢                    i                                                              +                              Δ                ⁢                                                                  ⁢                                  t                                                            2                      ⁢                                                                                          ⁢                      i                                        +                    1                                                                                =                                                    Δ                ⁢                                                                  ⁢                                  t                                      2                    ⁢                                                                                  ⁢                    i                                                                              Δ                ⁢                                                                  ⁢                                  T                  i                                                      .                                              (        1        )            The switch may be controlled by a two-level switch control signal such that one level of the control signal (e.g., the upper level) puts the switch in position 1, and the other level (e.g., the lower level) puts the switch in position 2. It may be shown that a properly defined duty cycle of the control signal would be equal to the duty cycle of the switch.
For example, for a “desired” (ideal) switching voltage regulator, the relation between the output voltage Vout(t) and a constant input (source) voltage Vin(t)=Vin=const, for a time-invariant (constant) load in a steady state such that ΔTi=ΔT=const and Di=D=const, may be expressed asVout(t)ΔTi=f(Di)Vin,  (2)where f(Di) is a known function of the duty cycle Di and the angular brackets denote the time averaging over a full switching interval. In words, for every full switching interval, the average output voltage of an ideal switching voltage regulator would be proportional to the source voltage, and the coefficient of proportionality would be a known function of the duty cycle of this interval.
FIG. 1 provides examples of such basic SMPS topologies (buck, boost, and buck-boost). For these topologies, f(D) in equation (2) would be equal to Di for a buck (step-down) regulator, to Di−1 for a boost (step-up) regulator, and to Di/(1−Di) for a buck-boost.
One may notice that the voltage at the pole of the switch in FIG. 1 is denoted as V*(t). This voltage may be called a switching voltage, or a modulated voltage. Indeed, this voltage alternates between Vin and zero in the buck converter (panel I), between Vout and zero in the boost converter (panel II), and between −Vin and Vout in the buck-boost converter (panel III). Depending on a physical implementation of a switch (e.g., one of the throws of a switch may be a nonlinear component such as a diode), the values of the alternating voltages may differ from the “ideal” values. However, the voltage at the pole of a switch may still be called a switching voltage, or a modulated voltage.
One skilled in the art will recognize that the SMPS topologies shown in FIG. 1 may be varied in many ways, and that they provide a basis for constructing most of isolated and non-isolated SMPSs [4, 7, 10]. For example, by adding a second inductor, the Ćuk [2] and SEPIC [9] converters may be implemented, or, by adding additional active switches, various bridge converters may be realized.
While equation (2) may hold for the average output voltage over a full switching period, the instantaneous value of the output voltage Vout(t) may be pulsating or even “discontinuous” (e.g., for the boost and buck-boost converters in FIG. 1). However, most practical applications would require that the instantaneous value of the output voltage Vout(t) does not significantly deviate from some desired (designed) output, for example, a constant DC voltage.
For the steady conditions outlined above, equation (2) may be rewritten asVout(t)=f(Di)Vin+δV(t),  (3)where δV(t) is a residual (“ripple”) voltage that, for a given switching frequency, may be negligible for sufficiently large capacitance values in the topologies shown in FIG. 1, and/or a sufficiently large inductance value in the buck converter.
For example, the current supplied to the parallel RC circuits in the boost and buck-boost topologies in FIG. 1 would be discontinuous (zero during the “up” positions of the switch, and generally non-zero during the “down” positions). The current through the load resistance R, for a constant load, would be equal to this discontinuous current filtered with a 1st order lowpass filter having the time constant RC, and thus the output voltage would satisfy equation (3), and the residual (ripple) voltage may be negligible for sufficiently large values of RC.
In the buck topology, the LCR circuit forms a 2nd order lowpass filter which may convert the discontinuous supply voltage (Vin during the “up” positions of the switch, and zero during the “down” positions) into a continuous output voltage that would satisfy equation (3). For zero capacitance, the remaining RL circuit would be a 1st order lowpass filter with the time constant L/R, and thus the output voltage would still satisfy equation (3).
In the buck topology, it may be convenient to refer to the LC sub-circuit of the total LCR circuit formed by the inductor, the capacitor, and the load as a “lowpass filter formed by the inductor and the capacitor”. For light loads (i.e. R→∞), such an LC sub-circuit would be effectively equivalent to the total LCR circuit.
FIG. 2 provides an example of steady-state outputs of the basic idealized converters shown in FIG. 1, operating at a 50% duty cycle. One may see that these steady-state outputs may indeed satisfy equation (3).
For a constant duty cycle, a steady-state output of a converter would be proportional to the input voltage. For a time-variant input voltage, the output voltage of a converter would also be time-variant, but it will not be, in general, proportional to the input voltage. In addition, for a time-variant load R=R(t) the output voltage would generally depend on the load resistance R(t) and its time derivative {dot over (R)}(t), and would be time-variant even for a constant load. A combined effect of the variability of the source voltage and the load may result in a significant deviation of the output from the desired steady-state conditions, as illustrated in FIG. 3. In the figure, the input voltage deviating from the average input voltage V0 is shown in the upper panel, and the time-variant load resistance is shown in the middle panel. The lower panel shows the output voltages of the buck, boost, and buck-boost converters shown in FIG. 1, operating at a 50% duty cycle, and the respective “would-be” steady-state outputs (that is, the outputs for Vin(t)=V0 and a constant load) are shown by the dashed lines. The switching frequency and the inductor and capacitor values are the same for all three converters.
Time variance of the output for time-variant input voltages and loads may be exacerbated by non-idealities of the components of an SMPS, such as finite switch conductances and/or voltage drops and/or switching times, equivalent series resistances of inductors and capacitors, parasitic inductances and capacitances of the components, and other non-idealities of components and non-linearities of their behavior (e.g. dependences of the component values on voltages and/or currents).
The output voltage may be regulated to be within a specified range in response to changes in the source voltage and/or the load current by adjusting the duty cycle to make the output voltage follow the desired (or “designed”, or “reference”) voltage Vref. This would be typically done by, first, constructing a small signal model of the converter linearized around some chosen operating point. Then a compensator may be designed based on the small signal model.
Such a compensator, however, may not ensure adequate performance when the conditions change significantly from the design operating point, for example, due to wide-range and/or significantly rapid changes in the source voltage and/or the load conductance. Thus one of the main limitations of such regulation, contributing to its complexity and/or inadequate performance under certain conditions, may be viewed as arising from the fact that the regulation is performed by a single means (e.g., a change in the duty cycle), while the output voltage (for a given duty cycle) may depend on two independently varying signals, the source voltage and the load (their magnitude and/or time variance).